System and method for forward error correction

ABSTRACT

Prior to transmission, data bits are arranged into matrices having blocks sized in accordance with a size or rate of an error burst. The matrices are arranged into an ordered set having first and second dimensions. One or more sets of check bits are generated for each block of data bits. At least one set of first check bits relates to the first dimension, and at least one set of second check bits relates to said second dimension. The ordered set of matrices is transmitted across a transmission channel and received at a decoder-corrector. One or more errors in data bits of the ordered set of matrices are detected and corrected, by the decoder-corrector, based on the check bits.

CROSS-REFERENCE TO RELATED APPLICATION

The present application claims priority to U.S. Provisional ApplicationNo. 60/364,894, entitled “System and Method for Adaptable Forward ErrorCorrection,” filed Mar. 14, 2002, the contents of which are herebyincorporated herein in their entirety by reference.

FIELD OF THE INVENTION

The present invention is directed to systems and methods for performingforward error correction, including adaptable forward error correction.

BACKGROUND OF THE INVENTION

U.S. Pat. No. 3,562,709 issued Feb. 9, 1971 to C. V. Srinivasan, isdirected to the correction of block errors in transmission of data. InSrinivasan, the matrix used to describe the mathematics for the codearithmetic corresponds to an arrangement similar to that given in theFIG. 1. The principal difference between the Srinivasan matrix and thematrix of FIG. 1, is that the Srinivasan matrix only used one zero oneach side of the check bit to separate it from the two arrangements ofthe data bits. Such an arrangement will work as a block error encoderand a block error detector, locator and corrector. However, thisarrangement, suffers from at least two drawbacks. First, under someconditions, errors occurring simultaneously in two blocks can bemisinterpreted as a group of errors in a third, totally different,block. Second, under other conditions, errors occurring simultaneouslyin two blocks can be misinterpreted as a situation where no errors arepresent at all.

Additional arrangements, where the additional zeros are interspersedwithin the set of data bits (while preserving the mirror imagearrangement of the Srinivasan patent), have been shown to have equallygood error detection, location and correction characteristics. Other newarrangements have also been shown to allow the construction of sets ofmatrices that have some particular total of data bits, such as 2^(N).

In the previous work described above, the mirror image arrangement ofthe data bits in a column was used. Also, there was never a case whereanything other than a regular arrangement of the check bits intopositions in the matrix was described. That is, the check bit in thefirst column of the matrix was assigned to some element such as thefirst, the middle or the last and the check bits of subsequent columnswere always arranged in a linear fashion going up or down (with awrap-around included as necessary) for the remaining columns.

U.S. Pat. No. 5,751,740 issued on May 12, 1998 to W. A. Helbig, Sr.,corrects the two limitations of the Srinivasan patent by using a matrixarrangement where there are two zeros on each side of the check bit ineach column. The Srinivasan patent also shows an identical number ofdata bits in each column of the matrix while the Helbig '740 patentshows that columns in the matrix may contain differing numbers of databits with additional zeros used to separate the check bit of a columnfrom the two images of the data bits in the column.

The code matrix shown in FIG. 1 has been constructed according to theteaching of the Helbig '740 patent. In this case, there are five databits, numbered D₁ through D₅, that have been placed respectively in thefirst five element spaces, numbers one through five, of the first columnof the matrix. In the next two element spaces, numbers six and seven,are each assigned the value zero. The next element space, number eight,is reserved for the eighth check bit, designated as C₈, that will becalculated as the modulo-two sum of the data bits that are put into theeighth element spaces of the other columns of the matrix. In the nexttwo element spaces, numbers nine and ten, are also each assigned thevalue zero. The last five element spaces, numbered eleven throughfifteen, are assigned, in reverse order, the values of the five databits, numbered D₁ through D₅, that have been placed respectively in thefirst five element spaces, numbers one through five, of the first columnof the matrix as shown.

Referring still to FIG. 1, the subsequent columns of the matrix areconstructed in a similar manner. The difference being, as taught in theHelbig '740 patent, that each subsequent column is circularly shifted byone row from the previous column.

When the placing of the entire group of data bits into the matrix iscompleted and all of the respective check bits have been calculated andplaced into the matrix the information is transmitted. The informationis sent by transmitting all of the data bits of the first column,numbered D₁ through D₅, and the Check Bit, numbered C₈, of the firstcolumn as a block of bits. This is followed by the transmission of theremaining blocks of data bits and check bit of the other columns of thematrix until all of the information has been sent.

Upon receipt of the information the error syndrome bits are calculatedusing the information received. If the error syndrome bits indicate thatthere are one or more errors in one of the blocks of bits received theinformation is corrected using the error syndrome bits. The Helbig '740patent contains the equations for determining whether one or more errorsare present in a column and how to fix the errors if such exist.However, if errors are found in more than one of the blocks of bitsreceived the errors cannot be corrected.

SUMMARY OF THE INVENTION

The present invention addresses the shortcoming of existing systems, andprovides for the correction of multiple errors in cases where errors arefound in more than one of the blocks of the received bits.

More particularly, the present invention is directed to a system andmethod of transmitting a plurality of data bits over a transmissionchannel. A plurality of data bits are arranged into a plurality ofmatrices, each of the plurality of matrices having a plurality ofblocks, wherein the plurality of data bits are arranged into theplurality of blocks. The plurality of matrices are arranged into a cubehaving a first dimension and a second dimension, the first dimensionrelating to one of the plurality of matrices, and the second dimensionrelating to multiple ones of the plurality of matrices. A set of checkbits are generated for each of the plurality of blocks in the matrices.Each set of check bits includes a first check bit and a second check bitwherein the first check bit relates to the first dimension of the cubeand the second check bit relates to the second dimension of said cube.One or more of the cubes are transmitted across a transmission channeland received at a decoder. The decoder detects and corrects one or moreerrors in data bits of cubes received at the decoder in accordance withthe check bits.

BRIEF DESCRIPTION OF THE DRAWINGS

The accompanying drawings, which are incorporated herein and constitutepart of this specification, illustrate the presently preferredembodiment of the invention, and, together with the general descriptiongiven above and the detailed description given below, serve to explainfeatures of the invention.

FIG. 1 illustrates a matrix used for implementing a forward errorcorrection system, in accordance with the prior art.

FIG. 2 illustrates a further matrix that can be used for implementing aforward error correction system, in accordance with the presentinvention.

FIG. 3 illustrates a further matrix that can be used for implementing aforward error correction system, in accordance with the presentinvention.

FIG. 4 illustrates a further matrix that can be used for implementing aforward error correction system, in accordance with the presentinvention.

FIGS. 5 and 6 illustrate further matrices that can be used together forimplementing a forward error correction system, in accordance with thepresent invention.

FIG. 7 depicts the order of transmission for the matrices shown in FIGS.5 and 6, in accordance with the present invention.

FIG. 8 illustrates a further matrix that can be used for implementing aforward error correction system, in accordance with the presentinvention.

FIG. 9 depicts the order of transmission for the matrix shown in FIG. 8,in accordance with the present invention.

FIG. 10 illustrates a “Part 1” matrix used for implementing a forwarderror correction system, in accordance with the present invention.

FIG. 11 illustrates a further matrix that can be used for implementing aforward error correction system, in accordance with the presentinvention.

FIG. 12 illustrates a further matrix that can be used for implementing aforward error correction system, in accordance with the presentinvention.

FIG. 13 illustrates a cube of data bits formed by combining the matricesof FIGS. 10, 11, 12, along with 12 further similarly constructedmatrices, in accordance with the present invention.

FIG. 14 is a diagram illustrating the method for computing check bitsfor the cube of data bits of FIG. 13, in accordance with the presentinvention.

FIG. 15 depicts the order of transmission for the cube of data shown inFIG. 13, in accordance with the present invention.

FIG. 16A depicts a correctable burst error covering multiple columns inone part, in accordance with the present invention.

FIG. 16B depicts a correctable burst error covering multiple columns inmore than one part, in accordance with the present invention.

FIG. 16C depicts an uncorrectable burst error covering multiple columnsin more than one part, in accordance with the present invention.

FIG. 16D depicts an example of multiple correctable burst errors, inaccordance with the present invention.

FIG. 17 is a further illustration of the cube shown in FIG. 13, inaccordance with the present invention.

FIG. 18 illustrates an exemplary encoder for generating the cube of FIG.17, in accordance with the present invention.

FIG. 19 illustrates a system for encoding and decoding data inaccordance with the present invention.

Throughout the figures, unless otherwise stated, the same referencenumerals and characters denote like features, elements, components, orportions of the illustrated embodiments.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT

Although the Helbig '740 patent contains the equations for determiningwhether one or more errors are present in a column and how to fix theerrors if such exist, questions remain as to why this arrangement shownin the Helbig '740 patent works and are there any other arrangementsthat work. No known mathematical analysis has been performed on thismethodology to prove that this arrangement will always work. However, byexamination and by trial and error certain facts about this techniquehave been discovered. One is that, for this arrangement, the two numbersof column elements between the two copies of each data bit are uniquefor all data bits. That is:

-   -   A. Between the two D₁ data bits there are zero elements in one        direction and thirteen elements in the other direction,    -   B. Between the two D₂ data bits there are two elements in one        direction and eleven elements in the other direction,    -   C. Between the two D₃ data bits there are four elements in one        direction and nine elements in the other direction,    -   D. Between the two D₄ data bits there are six elements in one        direction and seven elements in the other direction, and    -   E. Between the two D₅ data bits there are eight elements in one        direction and five elements in the other direction.        It can also be seen that this unique arrangement will always        prevent the two copies of one data bit from ever being in        positions that correspond to the two copies of any of the other        data bits in the matrix.

The arrangement of the data bits and the check bits into the matrix asshown in the FIG. 1 is not the only arrangement that can be used toconstruct the matrix. For example, the arrangement in FIG. 2 could alsobe used. However, upon close examination it can be seen that all of thecheck bit generation equations are the same for FIG. 1 and FIG. 2. Thisis easily seen to be true and the reason is that the FIG. 2 arrangementis one where the elements of all columns of the matrix are simplycircularly shifted vertically by one bit position (and the same will betrue for any other number of bit positions up to fourteen). It can alsobe easily seen that the same sort of thing will be true if the elementsof the rows in the matrix are circularly shifted one bit position (ormore up to fourteen bit positions) to the right or the left. This latterversion simply changes the subscripts of the data bits associated withthe check bit in a particular row as the columns are moved around. Thatis done so that, if the first column is always filled with the firstdata bits that arrive at the encoder and so forth the data bits have theproper notations.

Referring now to FIG. 3, there is shown an arrangement of the data bitsand check bits into a matrix that is different from the others so fardiscussed. However, it can easily be seen that the FIG. 3 matrix willpreserve the error correction capabilities of the FIG. 1 arrangement bysimply noting that there is one and only one check bit in each columnand in each row of the matrix. In fact, from this it can be seen thatany arrangement that preserves these properties and keeps thearrangements of the data bits in the columns so that the elements in allcolumns are palindromes (as they are in FIGS. 1 and 2) will providesimilar error correction characteristics.

FIG. 4 illustrates a further matrix that can be used for implementing aforward error correction system, in accordance with the presentinvention. What can be seen from an examination of this figure is thatit appears to be true that if any other positions of the data bits areused where the uniqueness of the distances between the two instances ofeach given data bit is preserved the same properties for errorcorrection will also be preserved. Such an arrangement can beconstructed by applying a circular shift to the data bits on one side ofthe column. For example, if a circular shift of three bits is applied tothe bottom data bits in the group position assignments, as shown in FIG.4, the distances between the two copies of the data bits then become asfollows:

-   -   A. Between the two D₁ data bits there are three elements in one        direction and ten elements in the other direction,    -   B. Between the two D₂ data bits there are five elements in one        direction and eight elements in the other direction,    -   C. Between the two D₃ data bits there are two elements in one        direction and eleven elements in the other direction,    -   D. Between the two D₄ data bits there are four elements in one        direction and nine elements in the other direction, and    -   E. Between the two D₅ data bits there are six elements in one        direction and seven elements in the other direction.        The same holds true for one, two and four bits of circular shift        as well.

FIGS. 5 and 6 illustrate further matrices that can be used together forimplementing a forward error correction system, in accordance with thepresent invention. In this case, the first set of data bits received areput into the first column of the first of two matrices that are used forthe first of two sets of calculations used with this arrangement. Hencethe check bit is designated C_(8A). (See FIG. 5.) The next set of databits received are put into the first column of the second of twomatrices that are used for the second of two sets of calculations usedwith this arrangement. Hence the check bit is designated C_(8B). (SeeFIG. 6.) This arrangement is continued until the entire matrices ofFIGS. 5 and 6 are completed by the calculation of all of the check bitsof the two matrices. When the information in the two matrices aretransmitted the data bits and the check bit of the first column of thefirst matrix (FIG. 5) are sent first (as is shown in FIG. 7). The databits and the check bit of the first column of the second matrix (FIG. 6)are sent next (as is also shown in FIG. 7). This process is thencontinued, as is diagrammed in FIG. 7, until all of the bits, both databits and check bits, are sent.

Using the illustration on FIG. 7, it can be seen that, if a burst oferrors whose length in bits is no more than one greater than the numberof bits (data and check bit) in one column of one matrix the error burstcan fall anywhere in the sequence of sending the bits without affectingany of the bits of either matrix except those in one, and only one,column. (If either of the matrices contains different numbers of databits in its various columns then this number must be equal to thesmallest number of bits in any column of either matrix.) This conditionis such that, using the error location and correction equations given inthe Helbig '740 patent, all of the bits in error can be corrected.

This arrangement of FIGS. 5-7 can be used for a larger number ofmatrices if protection from a larger burst of errors is to be achieved.Whatever number of matrices is used the maximum error burst length, inbits, that can be corrected will be equal to one bit plus a number ofbits that is equal to one less than the number of matrices usedmultiplied by the number of bits (data and check bit) in each column ofthe matrices. If the matrices contain differing numbers of data bits intheir various columns then this product will be equal to the smallestsum of the number of bits in each set of columns from the matrices thatare sent contiguously.

FIG. 8 illustrates a further matrix that can be used for implementing aforward error correction system, in accordance with the presentinvention. In this arrangement the data bits first received are put intothe first column of a matrix that is twice as wide as it is tall. Thenext data bits are then put into the second column of this matrix asshown, and so forth until the matrix is full. The check bits are thencalculated using the information in every other column for one set ofequations and the information in the other columns for the second set ofcalculations.

The data and check bits of the expanded width matrix in FIG. 8 are thentransmitted as shown in FIG. 9. This arrangement then produces the samecapability for correcting a burst of errors as the arrangement given inFIGS. 5-7, with the following exceptions:

-   -   A. The number of columns of the matrix must be an integer        multiple of the number of rows in the matrix, and    -   B. None of the factors of the number of rows in the matrix        (except 1) shall also be a factor of the integer specified in        exception A.        The reason for this is simply that these arrangements do not        preserve the condition that there be one and only one check bit        in each column and in each row of each of the matrices that are        interleaved in this manner. For example, if there were fifteen        rows in each matrix that is to be interleaved in this manner and        the number of matrices to be interleaved is either three or five        the “one and only one check bit in each column and in each row”        rule would not followed. For the three matrices case the first        check bit of the first matrix would be in row eight as shown.        The second check bit for this matrix would then appear in row        eleven, the next in row fourteen, the next in row two, the next        in row five and the next in row eight thus violating the rule.

FIGS. 1-9 are directed to code and matrix arrangements that can be usedfor block error correction and for single burst error correction. Theattributes of these arrangements are such that there is no theoreticallimit to the size of the matrices and, therefore, the size of the blockof errors that can be detected, located and corrected. With some of thetransmission interleaving arrangements described above, there is notheoretical limit to the size of the burst of errors that can bedetected, located and corrected. The limitation with the arrangementsdescribed thus far is that only one block of errors can be detected,located and corrected for each matrix and only one burst of errors canbe detected, located and corrected for each group of matrices used tomake up an EDAC frame. An EDAC Frame consists of those data bits andcheck bits that are combined by either interleaving or concatenation toproduce the burst error detection, location and correction capabilitydesired. If there are K data bits in each column of each matrix, theblock size is K+1 bits and there are 2*N+5 blocks in a matrix. If Lmatrices are combined to provide burst error detection, location andcorrection capability, then the maximum burst error length that can bedetected, located and corrected is equal to (L−1)*(K+1)+1 bits.

When the embodiments of FIGS. 1-9 are used for burst data transmission,a single EDAC Frame is sent during each transmission burst. When theembodiments of FIGS. 1-9 are used for continuous data transmission orfor long burst data transmission, multiple EDAC Frames are concatenatedand sent as a single entity. In the first case, a single error burst canbe detected, located and corrected during each burst of transmission.For the latter case, one error burst can be detected, located andcorrected in each EDAC Frame transmitted during each burst oftransmission.

The remainder of this disclosure describes an arrangement wherebymultiple matrices can be combined into a single EDAC Frame to achievethe capability to detect, locate and correct a collection of multiplebursts of errors that occur in a single EDAC Frame. The descriptionbelow is directed to the single case of a two dimensional arrangement ofblocks of bits. From this, an extension to the three dimensional case(as well as extensions to larger dimensions) will be understood by thoseskilled in the art.

Referring now to FIGS. 10-11, there is shown a further matrices that canbe used for implementing a forward error correction system, inaccordance with the present invention. The “Part 1” matrix of FIG. 10 isthe same as the matrix of FIG. 1 discussed above. The “Part 2” matrix ofFIG. 11 is constructed so that the check bits in the columns are inpositions that correspond to the next successive positions for checkbits in the same columns in the “Part 1” matrix of FIG. 10. That is, forexample, the check bit in the first column of the FIG. 10 matrix is inrow eight while the check bit in the first column in the FIG. 11 matrixis in row nine. Thus, the FIG. 11 matrix corresponds to the FIG. 10matrix with a circular vertical shift down of one element position (withthe appropriate wrap-around).

FIG. 12 illustrates a further matrix that can be used for implementing aforward error correction system, in accordance with the presentinvention. This matrix is constructed so that the check bits in thecolumns are in positions that correspond to the next successivepositions for check bits in the same columns in the matrix shown in FIG.11. That is, for example, the check bit in the first column of the FIG.11 matrix is in row nine while the check bit in the first column in theFIG. 12 matrix is in row ten. Thus, the FIG. 12 matrix corresponds tothe FIG. 11 matrix with a circular vertical shift down of one elementposition (with the appropriate wrap-around).

Twelve other matrices are also constructed in the same manner as thematrices of FIGS. 11 and 12, such that each successive matrix includes afurther vertical shift down of one element position (with theappropriate wrap-around).

FIG. 13 illustrates a cube of data bits formed by combining the matricesof FIGS. 10, 11, 12, along with the 12 farther similarly constructedmatrices, in accordance with the present invention.

FIG. 14 is a diagram illustrating the method for computing check bitsfor the cube of data bits of FIG. 13, in accordance with the presentinvention. For this arrangement, two check bit values are computed foreach column of each part. One value is calculated to be the modulo-twosum of the data bits in the check bit's row of the cube in the Xdimension as shown. The other value is calculated to be the modulo-twosum of the data bits in the check bit's row of the cube in the Zdimension as shown. That is, for example:

-   -   A. C_(18X)=D₂₀⊕D₂₄⊕D₂₈⊕D₃₂⊕D₃₆⊕D₄₁⊕D₄₇⊕D₅₃⊕D₅₉⊕D₆₅, and    -   B. C_(18Z)=D₅ [From the 4^(th) Part]⊕        -   D₄ [From the 5^(th) Part]⊕        -   D₃ [From the 6^(th) Part]⊕        -   D₂ [From the 7^(th) Part]⊕        -   D₁ [From the 8^(th) Part]⊕        -   D₁ [From the 9^(th) Part]⊕        -   D₂ [From the 10^(th) Part]⊕        -   D₃ [From the 11^(th) Part]⊕        -   D₄ [From the 12^(th) Part]⊕        -   D₅ [From the 13^(th) Part].

FIG. 15 depicts the order of transmission for the cube of data shown inFIG. 14, in accordance with the present invention. As shown in thefigure, all of the bits; data and both check bits, of the first columnof the Part 1 matrix are transmitted first. This is followed by thetransmission of all of the bits; data and both check bits, of the secondcolumn of the Part 1 matrix. This sequence is then followed until all ofthe bits; data and both check bits, of all of the columns of the Part 1matrix are transmitted. An identical sequence is then followed totransmit all of the bits; data and check bits, of the entire Part 2matrix. This sequence is then followed until all of the fifteen parts ofthe cube are transmitted. It should be noted that the bits; data andcheck bits, of the cube can, as an alternate approach, be transmittedusing a sequence that transmits, one right after the other, all of thebits; data and check bits, of the first column of all of the fifteenparts of the cube. In both cases, the multiple burst error correctioncapabilities of the cubic arrangement are the same.

FIGS. 16A-D illustrate how errors are handled in connection with thetransmission of the cube of data bits described above. FIG. 16Aillustrates a single burst of errors that occurs while the bits; dataand check bits, of the Part 1 matrix are being transmitted. For eachblock of bits that contain errors, detection, location and correctionwill result from the processing of the data and check bits in the Zdimension. Therefore, the burst of errors can cover the entire Part 1matrix and still be corrected. It will also be understood that theerrors of the burst can wrap around the end of the Part 1 matrix and onto the beginning of the Part 2 matrix, while not affecting the samecolumns of both the Part 1 and the Part 2 matrices and still becorrected through the processing of the data and check bits in the Zdimension.

Further, as illustrated in FIG. 16B, it will also be understood that theerrors of the burst can wrap around the end of the Part 1 matrix and onto the beginning of the Part 2 matrix, and affect only one of the samecolumns of both the Part 1 and the Part 2 matrices and still becorrected through the processing of the data and check bits in first theZ dimension and then in the X dimension. In this case, processing thedata and check bits in the Z dimension first will eliminate all of theerrors in columns two through fifteen of the Part 1 matrix leaving onlyerrors in columns one of both the Part 1 and Part 2 matrices. Then,processing the data and check bits in the X dimension will eliminate allof the errors in these two columns of both the Part 1 and the Part 2matrices.

As illustrated in FIG. 16C, if the error bursts affect two or more ofthe same columns of two or more of the fifteen parts of the cube, theseerrors cannot be corrected using the two dimensional arrangement for thecheck bits. In this case, when the data and check bits are processed inthe Z dimension, both of the equation sets for these two columns willboth indicate the presence of an uncorrectable error condition. Then,when the data and check bits are processed in the X dimension thecorresponding two parts of the cube will both still indicate thepresence of an uncorrectable error condition because the first errorcorrection processing did not remove enough errors to reduce the numberof columns affected by the errors to one or none for these parts of thecube.

FIG. 16D illustrates one example where multiple bursts of errors canoccur in the data of the cube and still be corrected. In this case, whenthe data and check bits are processed in the Z dimension, all of theerrors numbered one, two, four, five, six, eight, ten, twelve thirteen,fourteen, and fifteen will be corrected. Then when the data and checkbits are processed in the X dimension, the corresponding two parts ofthe cube will both still indicate the presence of errors in columneleven because the first error correction processing did not removethese errors. However, both of the second set of error correctionprocesses will, for Part 1 and Part 2 of the cube, indicate that theerrors present can be corrected and will do so.

Referring to the Code arrangement for correcting multiple error burststhat was described previously in described in connection with FIGS. 8-14above, it was stated that the check bits for each block (each column inthe Z direction of each plane in the X and Y dimensions) of the cube arecomputed both in the X dimension and in the Y dimension using theformulae described. The computations for the direction corresponding tothe direction that data comes into the Encoder are performed in the samemanner they would be if only one matrix (one plane) was being encoded.These computations can be performed as the data comes into the Encoderwith the full set of check bits fully computed almost immediately afterthe last column's data arrives at the Encoder. The same follows true forall of the columns in the same dimension.

As shown in FIG. 18, the implementation approach for performing theseencoding computations can be constructed using two registers. The firstregister is an Assembly Register that has the same number of stages asthere are entries in the columns of the cube (illustrated in FIG. 17.)The input data is loaded in this register in the same manner as isdiagrammed in the previous figures; i.e., two copies of each data bitare put into the Assembly Register in what can be the “mirror imagearrangement” illustrated in FIG. 1 or in any of the other arrangementsillustrated in the other figures. The second register is a CircularShift Register with the same number of stages as the Assembly Register.Connecting the two registers together is a set of Exclusive OR gateswith each having, as one of its two inputs, the output from one of thestages of the Assembly Register and, as the other of its two inputs theoutput from the corresponding stage of the Circular Shift Register. Theoutput of each of the Exclusive OR gates is connected to the input ofthe next successive stage of the Circular Shift Register as illustratedin FIG. 18.

After each set of M input data bits for each column of the X dimensionplane is put into the Assembly Register, its values are Exclusively ORedwith the previous contents of the Circular Shift Register as illustratedin FIG. 18 and the data bits that were put into the block of the matrixthat makes up the X dimension plane the data bits are stored into theproper location (s) of the Encoder's Data Memory. After all of the Msets of data bits in turn are put into the Assembly Register,Exclusively ORed with the previous contents of the Circular ShiftRegister as shown, and then stored into the appropriate locations of theEncoder's Data Memory, the final contents of the Circular Shift Registerare also stored into the appropriate location(s) of the Encoder's DataMemory and the Circular Shift Register is then cleared (i.e., set to allzeros).

To encode the data (generate the check bits) for the Z planes the logicneeded is exactly the same as that previously described. In fact, onlyone Assembly Register is required because the functions of the AssemblyRegister are the same for both sets of encoding operations. For the Xplane computations, the Circular Shift Register retains its contents aseach of the M sets of data bits are assembled and processed and onlyafter all of the M sets of data bits are processed are the contents ofthe Circular Shift Register stored in the Encoder's Data Memory and theCircular Shift Register is cleared of the contents just stored. For theZ plane computations, the interim contents for the computations of the Zplane (that is, the contents presently in the Circular Shift Register)are stored into the appropriate location(s) of the Encoder's Data Memoryafter each block of data (i.e., column of the matrix) is processed andthe Circular Shift Register is loaded with the interim contents of thecomputations being performed for the next successive Z plane from theappropriate location(s) of the Encoder's Data Memory. This process canbe diagrammed as set forth in Table I below:

For the First X Plane:

Step 1:

-   For the first X plane: Matrix Column #1 ⊕ 0→Circular Shift Register    (Shifted by one bit position).-   For the first Z plane: Matrix Column #1 ⊕ 0→First set of Z plane    Encoder Data Memory locations.    Step 2:-   For the first X plane: Matrix Column #2 ⊕ Circular Shift Register    contents→Circular Shift Register (Shifted by one bit position).-   For the second Z plane: Matrix Column #2 ⊕ 0→Second set of Z plane    Encoder Data Memory locations.    Steps R=3 Through M-1:-   For the first X plane: Matrix Column #R ⊕ Circular Shift Register    contents→Circular Shift Register (Shifted by one bit position).-   For the R^(TH) Z plane: Matrix Column #R ⊕0<R^(TH) set of Z plane    Encoder Data Memory locations.    Step M:-   For the X plane: Matrix Column #M ⊕ Circular Shift Register    contents→First set of X plane Encoder Data Memory locations (Shifted    by one bit position).-   For the Z plane: Matrix Column #R ⊕ 0→M^(TH) set of Z plane Encoder    Data Memory locations.    For the Second X Plane:    Step 1:-   For the second X plane: Matrix Column #1 ⊕0→Circular Shift Register    (Shifted by one bit position).-   For the first Z plane: Matrix Column #2 ⊕ Previous contents of the    first set of Z plane Encoder Data Memory locations→First set of Z    plane Encoder Data Memory locations.    Step 2:-   For the second X plane: Matrix Column #2 ⊕0→Circular Shift Register    (Shifted by one bit position).-   For the second Z plane: Matrix Column #2 ⊕ Previous contents of the    second set of Z plane Encoder Data Memory locations→Second set of Y    plane Encoder Data Memory locations.    ETC.

TABLE I

After an area of the Encoder's Data Memory is filled with the data andcheck bits for one EDAC cube, another area is then used to assembly thedata and check bits for the next sequential EDAC cube. While the Encoderis generating the check bits for this next EDAC cube, the data and checkbits for the previously assembled EDAC cube can be transmitted. Byvirtue of the system clocks being properly set, the area of theEncoder's Data Memory that holds the data and check bits for thepreviously assembled EDAC cube will be emptied at the same time the areaof the Encoder's Data Memory that holds the data and check bits for theEDAC cube being assembled is filled. Thus, only two Encoder Data Memoryareas are needed for the system to run continually. This will produce alatency for the Encoder that is equal to one EDAC frame time.

With further analysis it can be shown that while the Encoder logic ishandling data for the M^(TH) X plane of an EDAC cube the data and checkbits for the 1^(ST) X plane for the previously assembled data and checkbits for this EDAC cube can be transmitted. This will produce a latencyfor the Encoder that is slightly less than one EDAC frame time.

When the data and check bits for an assembled EDAC cube are transmittedit does not matter whether the transmission sequence sends the data andcheck bits for each X plane in sequence or sends the data and check bitsfor each Z plane in sequence. Both arrangements, because of the use oftwo-dimensional check bit encoding, will have the same error detection,location and correction properties.

When data is transmitted using the order of sending all of the columnsof data and check bits from the first X plane before sending any otherdata and check bits, this is followed by sending all of the columns ofdata and check bits of the second X plane. This is then followed bysending all of the columns of data and check bits of the remaining Xplanes in order.

With this arrangement, whenever an error burst occurs it will affect thedata and check bits of one or more columns that are transmitted adjacentto each other. Often this will result in the processing of the receiveddata and check bits for the X plane determining that the data is notrecoverable. This is because more than one block of the matrix that isthe X plane contains errors. However, it will be understood that, evenin the extreme case shown in FIG. 16A, that all of the errors will becorrected when the data and check bits are processed in the Z planes.

Even if the error burst covers the of data and check bits shown in FIG.16B, the errors in the first X plane cannot be corrected by the X planeprocessing. Further, all of the errors of the first X plane cannot becorrected by the Y plane processing because there are errors in both thefirst columns of the first and second X planes. However, the errors inthe first column of the second X plane will be corrected when the Xplane processing is performed for this second X plane leaving just theerrors in the first column of the first X plane for the Z planeprocessing to clear up; which it will do.

From this it is easy to see that the errors in the first two columns ofthe first two X planes, as shown in FIG. 16C, cannot be corrected evenwith the processing performed in two dimensions. Processing in the Zplane direction will correct all of the errors in all of the columns ofthe first X plane from the third column on but it will leave doubleerror conditions for both of the first and second columns of the firstand second X planes. In fact, with this case it doesn't matter if theprocessing is done in the X plane direction first and then in the Zplane direction or vice versa. The results will still be the same. Theconclusion is then that the maximum burst error length cannot be anylonger than the length of one plane or such an uncorrectable errorsituation will likely arise.

If the error situation is as illustrated in FIG. 16D, processing firstin the X plane dimension will get rid of the errors in the 8^(TH) columnof the 3^(RD) X plane. Subsequent processing in the Y plane dimensionwill get rid of the errors in the 4^(TH), 5^(TH), 6^(TH), 12^(TH),13^(TH), 14^(TH) and 15^(TH) columns of the first X plane and the1^(ST), 2^(ND) and 10^(TH) columns of the 2^(ND) X plane. What willremain will be the errors in the 11^(TH) columns of both the 1^(ST) andthe 2^(ND) X planes, which, by the way, would both be removed by anadditional cycle of X plane processing.

It is not as easy to construct an example where a second round ofprocessing would be required in both the X plane and in the Z planedimensions to remove the final errors after the first sequence of Xplane processing and then Z plane processing is completed. Further, itwould seem to be possible to construct an example where a third round ofprocessing cycles would be required to remove the errors remaining afterthe first two rounds of processing have been completed. It can be seen,by the difficulty to construct such examples, that the errorcombinations will have to fall in very specific locations relative toeach other meaning that the probability of such cases occurring will bevery low. In fact, the probability will become lower as the difficultyto construct such cases grows.

In the examples discussed so far, the processing is said to be firstperformed in the X plane dimension. This is the dimension in which thedata and check bits are said to be transmitted. This is also thedimension in which multiple columns will be in error if the error burstcovers more than one column of data and check bits. However, it is alsothe dimension where the error processing can be done while the data andcheck bits are being received. Therefore, doing the processing in thesame plane dimension as the dimension used for transmitting the data andcheck bits will require a processing latency of just one EDAC frame timeto achieve. While, on the other hand; doing the first processing of thedata and check bits in the plane dimension opposite to the dimensionused for transmitting the data and check bits will require two EDACframe times to achieve.

From an implementation standpoint, doing the processing in the sameplane dimension as the dimension used for transmitting the data andcheck bits will require less hardware because theDecoder/Error-Locator/Error-Corrector Data Memory control system will bemuch simpler that that required for doing the processing in the oppositedimension as the dimension used for transmitting the data and checkbits.

From these illustrations it appears that the multiple burst errorprocessing should occur first in the Z dimension and then in the Xdimension. If similar illustrations are constructed for multiple bursterror conditions that could occur if the alternate transmission sequencedescribed in connection with FIG. 15 above were used, it would appearthat the best error processing would occur first in the X dimension andthen in the Z dimension. This indicates that the first set of errorcorrection processes should occur in the opposite dimension from the oneused to govern the data transmission sequence.

However, if other illustrations are constructed it is easy to show thatthis isn't necessarily true. What can be easily shown is that the bestway to process the received data to correct for multiple error bursts isto process the received data in the dimension opposite the one used forthe transmission sequence, then process the remaining data in the otherdimension, and then do both of these sets of processing over again.There are many arrangements of the errors in the matrices that can becorrected in this manner when they could not be corrected with the twoprocessing cycle approach.

The four processing cycle approach will undoubtedly be more expensive toimplement than the two processing cycle approach. Further, since theinherent error rate of the transmission channel is likely to be fairlylow, implementing the four cycle error correction approach will likelyprove to be totally uneconomical. Therefore, the four cycle errorcorrection approach is not recommended.

It should also be noted that even greater error detection, location andcorrection capabilities can be obtained by expanding the coding of thedata using three or more dimensions of check bits. Here as well, justbecause the mathematical processes can be formulated, it doesn't meanthat it is a viable solution that should be used. With just the twodimension encoding and the two dimensions of error detection, locationand correction processing used, the probability of having anuncorrectable error condition occur will be so low that it will beextremely expensive to try to do something other than detect theuncorrectable error condition and then ask for a re-transmission of thedata in the cube.

Finally, it is expected that the percentage of error situations thatwill occur that can be directly handled by these two choices ofprocessing sequences will be about the same. Therefore, since thesequence of first doing the processing in the same plane dimension asthe dimension used for transmitting the data and check bits will be lessexpensive, this arrangement is the preferred one. On the other hand, ifthe extra latency will not be a problem it may just be, because a singleIC implementation of the Decoder/Error-Locator/Error-Corrector unit willnot be expensive, that two of the Decoder/Error-Locator/Error-Correctorunits in series will be the most popular choice.

FIG. 19 illustrates a system for encoding and decoding data inaccordance with the present invention. As shown in FIG. 19, the systemconsists of two sections: an Encoder 1901 and a Decoder-Corrector 1902.Encoder 1902 applies an encoding algorithm as described above inconnection with FIGS. 8-18 to data that is provided by a generatingsource to receiver 1903. The encoding process is performed using encoder1904, and generates two sets of redundancy bits that are combined withthe input data to produce the encoded data. The encoded data is thensent via transmitter 1905 to the input interface for a communicationchannel, which conveys the encoded data to a selected terminal site. Atthe terminal site, the communication channel's output interface is usedto transfer the received encoded information to the Decoder-Correctorunit 1902 via receiver 1906. The Decoder-Corrector 1902 is formed of atleast one decoder-corrector 1902 a, and optionally furtherdecoder-corrector units such as unit 1902 b. The Decoder-Corrector unit1902 applies a decoding algorithm as described in above in connectionwith FIGS. 8-18 to the data that has been sent to it from thecommunication channel output interface. After the Decoder-Corrector 1902processes the received data, the recovered encoded data is thenreformatted back into the same format used by the generating source andsent to the input interface for a user unit.

A synchronization pattern generator logic unit 1907 interrupts the flowof the encoded data from the Encoder unit 1901 to the communicationchannel in order to insert the transmission of a synchronizationpattern. This pattern is conveyed to a synchronization pattern detectorlogic unit 1908 that accompanies the Decoder-Corrector 1902 to insurethat the operations of the Encoder 1901 and the Decoder-Corrector 1902are synchronized so that proper error detecting, locating and correctingoperations may be performed on the data received at the output of thecommunication channel.

Decoder-Corrector Unit 1902 provides four levels of outputs. The firstlevel of processing (Level 0) performed on the received bits is one thatsimply removes both levels of overhead bits, reformats the data bitsthat remain back into the format in which they were received and thentransmits the result over an RS-232C output channel via transmitter.When the channel error insertion rate is low, perhaps less than 10⁻⁵,this output can, and should be, used because it has the least processinglatency of all of the system outputs, approximately 0.01 second. As thechannel error insertion rate increases, up to about 10³, the first level(Level 1) of EDAC processing capability should be used. This will reducethe residue of errors to something less than 10⁻⁷ at the expense of anincreased latency, to approximately 0.11 second. As the channel errorinsertion rate increases to a severe value, up to about 5*10⁻², thesecond EDAC processing capability (Level 2) can be applied to theresults of the first EDAC processing level. Again the result will be areduction of the residual errors to something less than 10⁻⁷. Thecombined processing latency, however, will increase to be on the orderof 5.06 seconds.

For each processing level there is a separate RS-232C output channel. Inall cases the redundant bits are removed and the data bits arereformatted back to that used for the input. Internal to theDecoder-Corrector Unit 1902, errors in both the data and redundant bitsare corrected with each EDAC processing level. In both cases the formatof the encoded data is preserved at the processing output and the outputof the second processing level is sent to the Decoder-Corrector Unit'sfourth output port in the RS-232C format.

The FEC Decoder-Corrector 1902 a prepares the Level 1 output by usingthe X Plane check bits to recognize, locate and correct what errors itcan in the X Plane dimension, then removing the check bits, both the XPlane check bits and the Z Plane check bits, reformatting the data backinto the RS-232C standard, and outputting a result via transmitter 1910.

The FEC Decoder-Corrector Level 1 error recognition, location andcorrection logic, in correcting what errors it can, will correct boththe erroneous data bits and the X Plane check bits. The result of thisLevel 1 logic will be passed to the part of the FEC Decoder-Correctorlogic that will perform the Level 2, Z Plane, error recognition,location and correction operations. The FEC Decoder-Corrector 1902 aprepares the Level 2 output by using the Z Plane check bits torecognize, locate and correct what errors it can in the Z Planedimension, then removing the check bits, both the X Plane check bits andthe Z Plane check bits, and reformatting the data back into the RS-232Cstandard. The result of the Level 2 error recognition, location andcorrection operations is output via transmitter 1911.

The FEC Decoder-Corrector Level 2 error recognition, location andcorrection logic, in correcting what errors it can, will correct boththe erroneous data bits and the Z Plane check bits. A fourth output(1912) of Decoder-Corrector Unit 1902 a can be, if desired, connected tothe input of a second Decoder-Corrector Unit 1902 b for further EDACprocessing (Level 3). The processing output 1912 will, in oneembodiment, consist of the results of both the Level 1 and Level 2 errorrecognition, location and correction operations performed byDecoder-Corrector 1902 a. The results of these two sequentialoperations, along with the X Plane check bits and the Z Plane checkbits, are then reformatted according to the RS-232C channel standard andthen made available to the second FEC Decoder-Corrector's 1902 b viaoutput 1912. Output 1912 will be identical in format to what the firstFEC Decoder-Corrector 1902 a received as its input from theCommunication Channel; with fewer (and hopefully zero) errors. If thisoutput 1912 from the first FEC Decoder-Corrector 1902 a is connected tothe input of a second FEC Decoder-Corrector unit 1902 b then the sameLevel 0, Level 1, Level 2 and Level 3 processing will be performedwithin this second FEC Decoder-Corrector unit 1902 b producing anotherset of outputs. The Level 0 output (not shown) of this secondDecoder-Corrector unit 1902 b will be identical to the Level 2 output ofthe first FEC Decoder-Corrector unit. The Level 1 output of the secondFEC Decoder-Corrector unit 1902 b (Level 1 output of the secondDecoder-Corrector 1902 b corresponds to the “Level 3 Corrected Output”of Decoder-Corrector 1902 b in FIG. 19) will have undergone a secondround of X Plane error recognition, location and correction operationsand then reformatting for transmission to a computer, or other system.The Level 2 output of the second FEC Decoder-Corrector unit 1902 b(Level 2 output of the second Decoder-Corrector 1902 b corresponds tothe “Level 4 Corrected Output” of Decoder-Corrector 1902 b in FIG. 19)will have undergone a second round of X Plane error recognition,location and correction operations and subsequent Z Plane errorrecognition, location and correction operations and then reformattingfor transmission to a computer, or other system. As before, during boththe X Plane and the Z Plane error recognition, location and correctionoperations the X Plane check bits are corrected as is possible andretained and the Z Plane check bits are corrected as is possible andretained and the result is reformatted according to the RS-232C channelstandard and then made available as the second FEC Decoder-Corrector'sthird level output (1913), which could be, if it is wanted, sent to athird FEC Decoder-Corrector unit (not shown) for still furtherprocessing.

While the principles of the invention have been described above inconnection with the specific apparatus and associated methods set forthabove, it is to be clearly understood that the above description is madeonly by way of example and not as a limitation on the scope of theinvention as defined in the appended claims.

1. A method of transmitting a plurality of data bits over a transmissionchannel, said method comprising: (a) arranging the plurality of databits into a sequence of data blocks each composed of an equal number ofdata bits; (b) arranging a portion of the sequence of data blocks into afirst plurality of matrices, n, where each of said matrices has an equalnumber, y, of columns and rows, numbered 0 through y, where y is equalto twice the number of data bits in each data block plus an odd numberequal to at least five, by: (i) setting a first counter, i, equal toone; (ii) arranging a first block of data bits in segment i of thesequence in a column i of a first matrix of the first plurality ofmatrices; (iii) setting a second counter, j, equal to one: (iv)arranging a next block of data bits in segment i of the sequence incolumn i of a matrix, (j+i), of the first plurality of matrices inaccordance with the pattern used for arranging the data bits in column(j+i, modulo y+1) of the matrix, i, of the first plurality of matrices;(v) incrementing the second counter, j, by one; (vi) repeating steps(b)(iv)-(b)(v) until all matrices of the first plurality of matriceshave data bits in their columns i; (vii) incrementing the first counter,i, by one; and (viii) repeating steps (b)(iii)-(b)(vii) until allcolumns of all matrices of the first plurality of matrices are filledwith data bits; (c) generating one set of check bits, in a firstprocessing arrangement, for each matrix having a plurality of datablocks and being a part of the first plurality of matrices andassociating a corresponding check bit with the data bits of each blockof data of each matrix of the first plurality of matrices; (d) repeatingsteps (b)-(c) for a second plurality of matrices with the data bits ofthe first column of the first matrix of the second plurality of matricesarranged as the data bits in the n+1^(st) column of the first matrix ofthe first plurality of matrices, the first column of the second matrixof the second plurality of matrices arranged as the data bits in then+2^(nd) column of the first matrix of the first plurality of matrices,and continuing in a like manner until all columns of all matrices of thesecond plurality of matrices are filled with data bits; (e) generatingone set of check bits, in the first processing arrangement, for eachmatrix having a plurality of data blocks and being a part of the secondplurality of matrices and associating a corresponding check bit with thedata bits of each block of data of each matrix of the second pluralityof matrices; (f) repeating steps (d)-(e) for a third plurality ofmatrices with the data bits of the first column of the first matrix ofthe second plurality of matrices arranged as the data bits in then+1^(st) column of the first matrix of the second plurality of matrices,the first column of the second matrix of the second plurality ofmatrices arranged as the data bits in the n+2^(nd) column of the firstmatrix of the second plurality of matrices, and continuing in a likemanner until all columns of all matrices of the third plurality ofmatrices are filled with data bits; (g) generating one set of checkbits, in the first processing arrangement, for each matrix having aplurality of data blocks and being a part of the third plurality ofmatrices and associating a corresponding check bit with the data bits ofeach block of data of each matrix of the third plurality of matrices;(h) repeating steps (f)-(g) for additional pluralities of matrices inlike manners until sets of check bits are generated for each matrix ofall n matrices of all y/n pluralities of matrices; (i) generating asecond set of check bits, in a second processing arrangement, for amatrix whose columns correspond to the first columns of all of thematrices processed in steps (b)-(h); (j) generating a second set ofcheck bits, in the second processing arrangement, for a matrix whosecolumns correspond to the second columns of all of the matricesprocessed in steps (b)-(h); (k) repeating step (j) for all columns ofall matrices in the pluralities of matrices in like manners until ysecond sets of check bits for all matrices of all pluralities ofmatrices are generated; (l) transmitting at least an ordered set ofpluralities of matrices having an ordered set of data blocks and eachdata block having two associated check bits in an order that is the sameas an order in which the bits of the data blocks of each set ofpluralities of data blocks are processed by the first processingarrangement; (m) receiving at least said ordered set of matrices havingsaid ordered set of data blocks and each data block having twoassociated check bits at a decoder-corrector; (n) detecting andcorrecting in a first manner, with said decoder-corrector, one or moreerrors in the data bits or first check bit of the data blocks of saidordered sets of pluralities of matrices initially using the first setsof check bits generated for these data blocks according to the firstprocessing arrangement.
 2. The method of claim 1, wherein step (n)further comprises: detecting and correcting in a second manner, withsaid decoder-corrector, one or more errors that remain in the data bitsusing the second check bits generated for the data blocks according tothe second processing arrangement.
 3. The method of claim 2, whereinstep (n) further comprises: repeating the detecting and correcting inthe first manner, with said decoder-corrector, one or more errors thatremain in the data bits or first check bits of the data blocks of saidordered set of pluralities of matrices using corrected first sets ofcheck bits generated for the data blocks according to the firstprocessing arrangement.
 4. The method of claim 3, wherein step (n)further comprises: detecting and correcting in the second manner, withsaid decoder-corrector, one or more errors that remain in the data bitsor second check bits of the data blocks of said ordered set ofpluralities of matrices using corrected second check bits generated forthe data blocks according to the second processing arrangement.
 5. Themethod of claim 4, wherein step (n) further comprises: performing one ormore further iterations of the following steps: (i) detecting andcorrecting in the first manner, with said decoder-corrector, one or moreerrors that remain in the data bits or first check bits of the datablocks of said ordered set of pluralities of matrices using correctedfirst sets of check bits generated for the data blocks according to thefirst processing arrangement; and (ii) detecting and correcting in thesecond manner, with said decoder-corrector, one or more errors thatremain in the data bits or second check bits of the data blocks of saidordered set of pluralities of matrices using corrected second check bitsgenerated for the data blocks according to the second processingarrangement.
 6. The method of claim 1, where n is where n is equal tothree or more.
 7. The method of claim 6, where n is equal to an integerfactor of y.